As shown in FIG. 1, metal oxide semiconductor field effect transistor 10 (MOSFET) includes a source 13 and a drain 14 (connected respectively to source electrode 13a and drain electrode 14a) each with an impurity type opposite to the impurity type of the substrate 15. The source 13 and drain 14 are separated by a channel region in the substrate 15 underlying a control gate 11 formed over a dielectric layer 12 on top of the silicon substrate 15. When the voltage applied to the gate electrode 11a electrically connected to control gate 11 exceeds the threshold voltage of the MOSFET 10, the channel region in the substrate 15 between the source 13 and the drain 14 and just below the dielectric 12 under the control gate 11 of the MOSFET device 10 is inverted to the same conductivity type as the source 13 and drain 14 to make electrical connection between source 13 and drain 14. A non-volatile memory (NVM) cell stores information by placing charges in the storing material 12b between the control gate 11 and the channel region of the MOSFET 10. In FIG. 1, charge is shown as being stored in region 12b of dielectric 12 but it should be understood that the charge could be stored on a conductive floating gate in region 12b or in nanocrystals in the dielectric 12 such as the region 12c above 12b or the region 12a below 12b. Thus the storing material can be a conducting material such as highly doped poly-silicon, charge trapping dielectric such as a nitride film, or nano crystals. By placing charges in the storing material 12b in an NVM cell, the threshold voltage of the MOSFET device 10 can be altered. Various values of information can thus be stored in an NVM cell by placing various amounts of charge in the storing material 12b to alter the threshold voltage level of the NVM cell. The value of the information stored corresponds to the amount of charge stored which in turn can be determined by determining the threshold voltage of the MOSFET device 10 in the cell. The stored charges in an NVM cell are not volatile even when the power for the NVM device is turned off. The information stored in an NVM cell can be retrieved by determining and reading out the threshold voltage of the MOSFET 10 in the NVM cell.
To place different amounts of charge in the storing material 12b of an NVM cell is called “programming” or “writing”. In contrast, to erase an NVM cell, the stored charges must be removed from the storing material 12b. The method used to program an NVM cell has been based on three mechanisms: 1. Hot Carrier Injection (HCI); 2. Fowler-Nordheim (FN) tunneling; 3. Band-to-band tunneling (See. IEEE Std 1005-1998 and IEEE Std 641-1987). HCI and FN tunneling are the two most commonly used programming mechanisms for NVM devices. HCI is the fastest programming method to obtain the desired threshold voltage shift associated with MOSFET 10 in an NVM cell but uses large programming current, while FN tunneling uses little programming current but requires a longer programming time to achieve the desired threshold voltage shift.
Conventional HCI programming applies a relatively high voltage (greater than Vcc, the regular supply voltage applied to the memory during normal operation) to the drain electrode 14a and the control gate electrode 11a of the MOSFET 10 in an NVM cell, while the substrate 15 or source electrode 13a are connected to ground. In such a way, an inverted region 17 (i.e. a region with the same conductivity type as the source 13) is created in the channel region adjacent to the source 13 extending toward, but not reaching the drain 14. A depletion region 16 as shown in FIG. 1 is formed beneath the source 13, the inverted region 17, in the channel region directly beneath the gate electrode 11 but beyond the point 19 where the inverted region 17 ends (called the “pinch-off point”) and beneath the drain 14. A high lateral electric field is created in the depletion region 16 between the pinch-off point 19 and the drain electrode 14. As shown schematically in FIG. 1, the channel inversion layer 17 is wider near the source 13 and narrows as it approaches the pinch-off point 19. As the charge carriers current Is at the source side passes through the pinch-off point 19, the charges, now forming current Id at the drain side are strongly accelerated toward the drain 14 in the high field of the drain-depletion region (i.e. the portion of depletion region 16 between pinch-off point 19 and drain 14). As a result, the charge carriers are scattered in a direction such as to reach the Si/SiO2 interface (i.e. the interface between the silicon substrate 15 and the SiO2 (dielectric 12). The shape of the SiO2 (dielectric 12) energy barrier varies along with the channel length (i.e. the length of inversion region 17) due to the substrate 15 surface potential variation induced by the applied constant control gate 11 voltage and constant drain 14 voltage bias. Consequently, near the source electrode 13, the oxide field is very strongly biased toward the direction of gate 11 but with almost no available hot carriers for injection into the storing material 12b. While abundant hot carriers are generated near the depletion region between pinch-off point 19 and drain electrode 14, there is only a very small electric field from oxide 12 to substrate 15 (called the “oxide field”) near the pinch-off point 19 in the depletion-drain region (i.e. in the region between the pinch-off point 19 and drain 14) to collect the hot carriers, which form a weak substrate current Isub. Less than one per million of hot carriers is collected toward the oxide field and thus flows into storage material 12b. With injection of carriers from the source 13, a large number of secondary carriers generated in the depletion-drain region flow into the drain electrode 14 and fractions of them flow into the substrate 15. The programming efficiency is thus very low. The typical programming current flowing through the drain electrode 14 of MOSFET 10 in an NVM cell is around hundreds of microampere per cell and only a small fraction of the current flows to the charge storage material 12b. 
In the conventional wisdom, the applied drain voltage cannot be lower than 3.1 V, which is the oxide barrier voltage for electrons to move inside the oxide field, for programming the MOSFET 10 in an NVM device using the HCI scheme (See Kinam Kim and Gitae Jeong, ISSCC Tech. Dig, pp. 576-577, 2005). This conventional belief imposes the condition that the drain 14 voltage must be higher than 3.2 volts and the drain electrode 14a must be supplied with a higher voltage supply usually between 3.5 volts to 6 volts. While MOSFET devices are scaled down to a smaller geometry, the main voltage supply, Vcc is scaled down accordingly. For example, the main voltage supply is as low as 1 volt for the technology nodes in nanometer scale generations. Thus, in the conventional HCI programming scheme, charge pumping circuitry is required to supply voltages higher than Vcc to the drain electrode 14a of NVM cells. It becomes very challenging for charge pump circuit design to support a high current load while maintaining a constant higher drain 14 voltage bias during programming MOSFET 10 in an NVM cell. For parallel programming an array of NVM cells, the programming uniformity can also be compromised from the high voltage supply dropout due to high current load. Due to this programming voltage bias incompatibility with the main voltage supply Vcc (ie, the programming voltage must be higher than Vcc), a complicated high voltage decoder including high voltage level shifters in the bitlines of an NVM array is also required for selective bitline switching.